The development of the HTX Processor card will be completed, with first generation gateware (the software that implements the hardware that allows the user to communicate data and processes with neighbouring devices). This means that applications software will be able to be written to run on this board in a relatively easy way in subsequent years. It will be too early to have a substantial application running on this processor node, and that will be tackled during the next year, when the gateware is more mature.

A method of running high dynamic range arithmetic without floating point operations will be demonstrated, firstly simulated on a conventional processor, and secondly, on a FPGA (A Field Programmable Gate Array is a large collection of logic cells, whose interconnection to implement
a computational function can be changed when power is applied to the device. FPGAs are not ideal for floating point arithmetic as the FP processor uses a large number of the available gates.

A card with fast analogue sampling capability has been developed by a KAT-sponsored student, and the CHPC will hopefully produce a sophisticated gateware for this card. The card is attracting great interest from a number of universities in the United States and the United Kingdom. The gateware will share much of the functional characteristics of the gateware being developed for the HTX processor.

A training course in the use of the Maxwell FPGA computer at the Edinburgh Parallel Computer Centre (EPCC) is to be developed, with the intention of running at least one application on the machine. This will be done with the ACE Laboratory two-node FPGA machine for prototyping. The code is likely to be a correlator for Radio Astronomy and Radar applications.

Concerted efforts will be made to involve other tertiary higher institutions in student projects of the ACE Laboratory, aiming at attracting at least two M.Sc. or PhD registrations for 2009.

ACE plans to deliver two completed M.Sc. dissertations and at least four conference publications.

ACE plans to produce four M.Sc. dissertations. Due to the dynamic nature of the work in the ACE Laboratory, journal publications will be more difficult, but at least 6 conference publications will be produced. Success in peer review journals will depend on whether new algorithms suitable for FPGA computing can be developed.

ACE wants to attract local scientists to utilise ACE Laboratory technology experimentally by providing programming tools and expertise. These users should produce peer review publications. Further aims are to establish permanent research officers and at least two post-doctoral students, and to register at least two PhD studentships in the group.

A processor card, with Xilinx Virtex 5 devices for communications and processing has been designed for fabrication, integration and testing. The unit has Hypertransport and 10Ge communications ports. Gateware is also being developed to allow the card to be used easily by higher level compilers i.e. to interconnect multiple cards and exchange data with conventional processors. Staff members involved in this project are Mike Aitken and Nick Thorne.

The board has been designed, and board fabrication is in process. Gateware development will continue until the middle of 2009. The KAT Project and CHPC are providing studentships, and the CHPC provides board fabrication and test facilities. Xilinx has generously donated software and chips to the project.

The DiFx correlator is an open-source code for radio astronomy interferometic signal processing. The project at ACE Lab has profiled the code, and is modifying it to use different acceleration techniques. Those currently under investigation are:

Staff members involved in this project are Andrew Woods, Arjun Radhakrishnan, Michael Gorven and Janet Hewitson. Institutions involved in this project are CHPC, Karoo Array Telescope (KAT), EPCC

The DiFX Correlator has been profiled and some of the computationally heavy modules are being converted to run on the FPGA cards fitted to the Maxwell computer at the EPCC.

The Radar Remote Sensing Group at UCT has developed Gauss Newton tracking algorithms, as alternatives to the Kalman filter. The present implementation takes bearing and doppler measurements from a simulated TV receiver, and uses these measurements to track the state
vector of an aircraft in a common view between the TV transmitter and the receiver. The Gauss Newton is computationally more demanding than the Kalman filter, but has demonstrated very robust and accurate performance. A longer-term goal is to use multiple G-N filters to track multiple targets.

Staff members involved in this project are Joe Milburn, Norman Morrison. Institutions involved in this project are CHPC, South African National Defence Force (Project Ledger) (SANDF), UCT, University College London (UCL).

The code has been profiled, and methods for accelerating the profiles using Clearspeed processor cards are being tested.

Passive Coherent Location (PCL) is the background technology that provides target plots for tracking. Delay and doppler can be extracted by using direct reception of the TV or FM Radio transmitter signal as a filter of the signal from the region of interest that contains the target(s). The reference has to be successively doppler shifted to match putative targets, and when the doppler matches the target, a strong cross-correlation results. Since long time records are used to improve the signal to noise ratio, the computational load is extremely large. The use of Cell and FPGA computing to assist with this computation will be examined.

Staff members involved in this project are Michael Gorven, Sebastiaan Heunis, Yoann Paichard, Aadil Volkwin, Gunther Lange. Institutions involved in this project are CHPC, SANDF, UCT and UCL.

The signal processing framework has been formulated, and a simulator written. The project can now move towards implementing the signal processing. Another set of projects involves the building of receiver and antenna technology for a prototype system to attempt to detect aircraft using Cape Town International Airport.

In general purpose computing, the finite dynamic range of the word size of the machine is improved by using the ubiquitous IEEE Floating Point number representation. This allows the programmer to largely ignore the dynamic range required of the computer, albeit that the numerical
resolution is limited by the single or double precision word size. FPGAs have a limited set of logic cells available, and a floating point implementation uses up a large portion of the resources.

The scaled-fraction approach is a simplified way of setting the machine dynamic range at compile time, possibly using fewer of the cells from the FPGA. This project investigates this technology and applies it to FPGA algorithms as used in high-performance computation e.g. for spectral computation in FFT calculations. Staff members involved in this project are Janet Hewitson and John Collins. Institutions involved in this project are CHPC, Liverpool Hope University, SimCon Ltd.

Preliminary research is being carried out around previous implementations of this technology, and by the end of 2008 some code will have been tested in a simulation, and probably on a FPGA.