Announcements

CHPC Supercomputer Amongst the World’s Best

6 February 2012

The Centre for High Performance Computing’ Sun Tsessebe Constellation System has yet again rejoined the world’s fastest supercomputers, this after the LINPACK Nenchmark placed it 329th in the international Top 500 list.

This prestigious accolade follows shortly after a marathon R9-million upgrade of the cluster conducted by a team from the CHPC, Cambridge University and Eclipse Holdings. The upgrade took three weeks and plenty of sacrifice as many nights and weekends were spent at the office with members taking turns to go home for a few hours of sleep. Even Research Scientist, Nicholas Thorne, rolled-up his sleeves and joined the graveyard shift, guided by technicians. For most of the CHPC team, this was their first upgrade on a system of this magnitude. Some had been involved in installations and upgrades of a smaller scale. The operation didn’t come without challenges, “There were times we had to wait for equipment that was withheld by customs or that overcame infrastructure restrictions. Fortunately due to the experience of the team other tasks were pushed forward and plans to overcome delay threats were put in place,” notes Albert van Eck, CHPC Systems Engineer. The most daunting task, they all agreed, was the labelling and installation of cables. Cables varied in size to minimize the length of slack and every cable was labelled according to its length and the predetermined position where it should be installed. This effectively meant labelling and installing 88 power cables, 176 network cables and 176 infiniband fibre cables. The dedication and commitment paid off when the performance of the machine improved from 21 to 61 Teraflops. The system is made up of Oracle’s Sunblade X6275 blades with Intel Nehalem 8 core processors and Westmere 12 core processors as well as Dell’s Poweredge C6100 servers with Intel Westmere 12 core processors. It has a theoretical peak performance of 74 Teraflops. Team work paid-off and all are ecstatic and proud to have been part of something of this magnitude. Sakhile Masoka, CHPC System Administrator, comments, “I work with Eclipse Holdings (Hellen and Langton); I know how hardworking and dedicated they are. Working with Cambridge and having their HPC Director, Dr Paul Calleja pulling cables and lifting boxes with me was very inspiring and gave me motivation and great passion for what I do. It feels good to know that what we do is of world standards.”

The improved performance of the cluster will boost the CHPC’s ability to service the African research community as usage of the system had almost reached full capacity, an indication of the CHPC’s commitment to providing a globally competitive, state of the art facility for research. The availability of local facilities for computational research that prioritise local needs and threats, provides an opportunity for possible solutions in the face of HIV/Aids, malaria, climate change, the search for renewable energies, industrial development and other local concerns. African researchers from academia and industry now have a facility that is able to process over 60 trillion cycles of instructions per second, enabling the CHPC to enhance significant research, address grand challenges and develop computational research into a viable mode across all academic disciplines.

CHPC Introductory Scientic Programming School

15 November 2011

A funded full-week Introductory Scientific Programming School for Science and Engineering students who wish to advance their skills in Linux (Ubuntu) and Python Programming language.

27 Nov. – 04 Dec. 2011

Hosted by the Centre for High Performance Computing (CHPC) of the Council for Scientific and Industrial Research (CSIR) at Meraka Institute and funded by the Department of Science and Technology (DST).

Syllabus to be covered includes:
Full 2 day on introduction to Linux (Ubuntu) on the following topics:

Overview of Ubuntu Linux Desktop; Running commands and Getting Help; Browsing the file system; the bash shell; Standard I/O and Pipe; Users, Groups and Permissions; vi and vim Editor basics; the Linux Filesystem In-Depth; Advanced Topics in Users; Groups and Permissions; Printing; Introduction to String Processing; String Processing with Regular Expressions; Finding and Processing Files; and Investigating and Managing Processes.

Full 4 days on Introduction to Python Programming on the following topics:

Python basics, Python Objects, Numbers, Sequences, Dictionaries, Conditional and Loops, Files and Input/Output, Error and Exceptions.

Download the full application form in MS Word format.

Download the full program for the school here

CLOSING DATE FOR APPLICATIONS: 18h00 Sunday 6 November 2011

Should you wish to become one of the participants, please complete the following application form and email (with e-mail subject: CHPC Introductory Programming School) the document back to: dmoeketsi@csir.co.za before the closing date. Successful candidates will be notified from 11 November 2011.

CSIR Executive Visits Rosebank Office

24 October 2011

Rosebank CSIR employees were honoured to welcome their executive leadership to their offices. The visit comes shortly after the extension of the CEO’s (Dr Sibisi) term of office by another five-years.

The executive's visit came as part of a series of roadshows targeted at all CSIR offices around the country. The leadership shared the CSIR's current status, the direction and plan of action for the next five years. In a commissioned study, it became clear that the community acknowledged the work the CSIR is doing, but that they wanted to see more impact emanating from the research. They also felt that CSIR research was widely spread over thin resources.

Dr Sibisi said for the next five years the CSIR strategic initiatives will not change in direction, but would be twicked, to enable the organisation to become more impact driven. He provided three flagships that the different components of the organisation should focus their planning on namely: Water Sustainability, Health and Nutrition and Safety and Security.

CSIR Rosebank employees were also given the opportunity to exchange ideas with the executive on how the organisation could become have more impact.

Moroccan Delegation Visits the CHPC

24 October 2011

The Moroccans special interests in South Africa's information and communication technologies, high computational facilities, bioprospecting, nanotechnology and photonics led them to the Meraka Institute and the CHPC. The delegation visited the centre to get a glimpse of its infrastructure, understand the nature of the research the centre facilitates and to hopefully initiate future collaborations with the CHPC.

Members of the delegation included the honourable Rachid Benmokhaar Benabdallah, previous Minister and current President of the Human Observatory of the Kingdom of Morocco and Adviser to His Majesty Mohamed VI and Prof Zouheir Sekkat, Director of the Moroccan Foundation for Advanced Science, Innovation and Research's (MASCIR) Centre of Photonics.

Morocco's proximity and special relations to Europe make it a strategic African nation of interest to the CHPC. Deliberations at the gathering bordered on the possibility of various collaborations the two countries could engage in from teleconferencing, which is a great challenge given Africa's low network availability, to data-curation and the possible exchange of fellows between the two countries for the sharing of best practises.

Discussions are hoped to culminate in a memorandum of understanding between the two nations.

Invitation: Parallel Processor Architecture and Parallel Computing

21 July 2011

From 3–5 August 2011 the CHPC will host a lecture series on Parallel Processor Architecture and Parallel Computing by Peter McMahon. Discussions will centre around the design of modern microprocessors (which now exploit parallelism in a variety of ways), and try to understand the impact of computer design on the performance of software.

The course will introduce parallel programming on multi-core processors and on clusters. We will also study GPU accelerations of computer programs, especially scientific codes. In particular we will try to understand, “Where do parallel speedups come from?”, and “What are the limits to speedups on different architectures?”.

Specific topics we may cover are:

• A review of traditional computer architecture
• Caching, memory and compiler optimizations for single-core CPUs
• Parallel programming using Pthreads and OpenMP
• Finding and exploiting parallelism, including case studies
• Shared memory multi-core processor design
• Acceleration using GPUs and FPGAs

There will be a series of practical exercises to reinforce the concepts taught during the lectures.

Intended Audience
The course is open to:

• Computer Science
• Electrical Engineering
• Computational science (Physics, Bioinformatics, Climate Science, Applied Mathematics, etc.)
• Undergraduate and postgraduate students, and researchers.

Required Background:

• Proficiency in C/C++ programming.
• Basic understanding of computer architecture.
• Basic understanding of linear algebra.

About the lecturer:

Peter McMahon is currently a research assistant at Stanford University. His most recent work is primarily on experimental quantum computation, but he continues to be involved in classical parallel computing and scientific computing research. Peter spent several months at the University of Illinois in 2006, and at the University of Edinburgh in 2007, working on reconfigurable computing for scientific applications. He subsequently spent a year at the University of California, Berkeley building radio astronomy instrumentation for pulsar and radio transient experiments, and an FPGA bioinformatics accelerator. He then spent a year at Stanford on a project to accelerate Deep Belief Nets using FPGAs. Peter graduated with a B.Sc. (Eng) in Electrical and Computer Engineering, an M.Sc. in Computer Science and an M.Sc. (Eng) in Electrical Engineering from the University of Cape Town. He received an M.S. in Electrical Engineering from Stanford University in 2010, where he is currently a Ph.D. candidate.

Scalable Parallel I/O Alternatives for Massively Parallel Partitioned Solver Systems

8 July 2011

On 15 July 2011 Professor Christopher Carothers from Rensselaer Polytechnic Institute, Department of Computer Science will be visiting CHPC to give a talk on Scalable Parallel I/O Alternatives for Massively Parallel Partitioned Solver Systems.

Abstract:

With the development of high-performance computing, I/O issues have become the bottleneck for many massively parallel applications. This paper investigates scalable parallel I/O alternatives for massively parallel partitioned solver systems. Typically such systems have synchronized ``loops'' and will write data in a well defined block I/O format consisting of a header and data portion. Our target use for such an parallel I/O subsystem is {\em checkpoint-restart} where writing is by far the most common operation and reading typically only happens during either initialization or during a restart operation because of a system failure. We compare four parallel I/O strategies: 1 POSIX File Per Processor (1PFPP), a synchronized parallel IO library (syncIO), ``Poor-Man's'' Parallel I/O (PMPIO) and a new ``reduced blocking'' strategy (rbIO). Performance tests using real CFD solver data from the PHASTA system show that the syncIO strategy can achieve a read bandwidth of 6.6GB/sec on Blue Gene/L using 16K processors which is significantly faster than 1PFPP or PMPIO approaches. The serial ``token-passing'' approach of PMPIO yields a 900MB/sec write bandwidth on 16K processors using 1024 files and 1PFPP achieves 600 MB/sec on 8K processors while the ``reduced-blocked'' rbIO strategy achieves an actual writing performance of 2.3GB/sec and {\em perceived/latency hiding} writing performance of more than 21,000 GB/sec (i.e., 21TB/sec) on a 32,768 processor Blue Gene/L.

Bio Chris Carothers is a Professor in the Computer Science Department at Rensselaer Polytechnic Institute. His research interest are in massively parallel systems focusing on modeling and simulation systems of all sorts. Prof. Carothers is an NSF CAREER award winner and is currently active in the DOE Exascale Co-Design Program associated with designs for next generation exascale storage systems as well as the NSF PetaApps Program, and the Army Research Center's Mobile Network Modeling Institute

15 July 2011

Japan reclaims title as supercomputer leader

21 June 2011

The eight-petaflop K Computer at the RIKEN Advanced Institute for Computational Science in Kobe, Japan, has won the title of fastest supercomputer in the new Top 500 Supercomputing List officially unveiled at the International Supercomputing Conference in Hamburg.

The K Computer, built by Fujitsu and RIKEN, consists of 672 computer racks equipped with a total of 68,544 SPARC64 CPUs. It achieved a measured 8.162 petaflops (quadrillion calculations per second) in the Linpack benchmark test — three times that of its nearest rival.

The K Computer's success allows Japan to reclaim the number one spot on the Supercomputing Top 500, which was last held in 2004 by NEC's Earth Simulator.

Second place on the new Top 500 list goes to last year's number one: Tianhe-1A, built by the National Supercomputing Center in Tianjin, China. In the latest benchmark, Tianhe-1A achieved 2.6 petaflops.

Source: RIKEN.

2011 HPC School

31 May 2011

The CHPC is pleased to announce its 3rd annual school in high performance computing.

The 2011 HPC School is a funded eight-day graduate course in parallel programming and high performance computing (HPC) for South African students who wish to advance their expertise in HPC and related research topics which would potentially rely on HPC techniques.

Delivered by renowned national and international experts in HPC this is an opportunity for graduate students in computational and quantitative sciences or engineering to expand their skills into supercomputing.

3 to 10 July 2011

For more information and to apply to attend the 2011 HPC School.

Applications are due 20 June 2011.

China claims the title for fastest supercomputer in the world

1 November 2010

The CHPC congratulates China on its new status as victor in the battle to build the fastest supercomputer in the world.

Already fully operational, the Tianhe-1A was unveiled recently at a national conference on high-performance computers in China. Tianhe, meaning Milky Way, has set a new performance record of 2.507 petaflops, or quatrillion calculations per second, making it the fastest system in the world, the title formerly held by the USA's Cray XT5 Jaguar system.

The technological achievement of the Tianhe-1A lies in the interconnect, or networking technology, developed by Chinese researchers that shuttles data back and forth at breakneck rates across the computer's individual processing units: 7,168 Nvidia Tesla M2050 graphics processing units (GPUs) and 14,336 Intel Xeon central processing units (CPUs).

The computer is the result of two years of work by 200 scientists at the National University of Defense Technology and is housed at the National Supercomputer Center in Tianjin. The center says it is “under the dual supervision of the Ministry of National Defense and the Ministry of Education.”

For more news and information on the Tianhe-1A see articles at the International Business Times and at the New York Times.